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commit
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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Binary file not shown.
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|
@ -0,0 +1,120 @@
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|||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "keyboard.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"0a2d6e55-042d-47d6-a3a9-519125c55c50",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,49 @@
|
|||
## Sketching out our address space
|
||||
|
||||
### Memory Map
|
||||
|
||||
CPU Addressable
|
||||
|
||||
| Address | Usage |
|
||||
| ------- | -------------------------------- |
|
||||
| `$0000` | 32k ram (16k addressable) |
|
||||
| `$1000` | ... |
|
||||
| `$2000` | ... |
|
||||
| `$3000` | ... |
|
||||
| `$4000` | I/0 & Hardware Control Registers |
|
||||
| `$5000` | ... |
|
||||
| `$6000` | 32k vram |
|
||||
| `$7000` | ... |
|
||||
| `$8000` | ... |
|
||||
| `$9000` | ... |
|
||||
| `$A000` | ... |
|
||||
| `$B000` | ... |
|
||||
| `$C000` | ... |
|
||||
| `$D000` | ... |
|
||||
| `$E000` | 32k eeprom (8k addressable) |
|
||||
| `$F000` | ... |
|
||||
|
||||
### Hardware Control Register $4000
|
||||
|
||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
||||
| --------- | ------------ | ------------ | -------- | ------------- | -------------------------- | ------ | ------ | ------ |
|
||||
| **Usage** | ROM Page MSB | ROM Page LSB | RAM Page | 32k Bank Page | Character/Hires Video Mode | Unused | Unused | Unused |
|
||||
|
||||
### Video Controls $4200 & $4201
|
||||
|
||||
When the system starts or when the video mode is changed, crt timing/character size information has to be sent to the 6845. This is done by writing
|
||||
|
||||
### Keyboard Rows $4300, $4301, $4302, $4303, $4304, $4305
|
||||
|
||||
Each keyboard row is mapped to a read-only 8-bit register, with each key mapped to a single bit. Due to the design of this keyboard, Row 5 has 5 unused bits
|
||||
|
||||
| Address | Desc | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|
||||
| ------- | ----- | --------- | ------ | ------ | ----- | ----- | ----- | ----- | ----------- |
|
||||
| `$4300` | Row 0 | `esc` | `w` | `e` | `r` | `t` | `u` | `o` | `backspace` |
|
||||
| `$4301` | Row 1 | `tab` | `q` | `s` | `g` | `y` | `i` | `p` | `enter` |
|
||||
| `$4302` | Row 2 | `shift` | `d` | `v` | `h` | `k` | `"` | `?` | `a` |
|
||||
| `$4303` | Row 3 | `control` | `z` | `f` | `b` | `j` | `l` | `2` | `4` |
|
||||
| `$4304` | Row 4 | `alt` | `x` | `c` | `n` | `m` | `'` | `1` | `3` |
|
||||
| `$4305` | Row 5 | `meta` | `sp 1` | `sp 2` | |
|
||||
|
||||
### Character ROM Layout
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
(kicad_sch (version 20230121) (generator eeschema)
|
||||
|
||||
(uuid 2e9cc28a-99d5-4284-9510-64062a6ace3b)
|
||||
|
||||
(paper "A4")
|
||||
|
||||
(title_block
|
||||
(title "ʕ·ᴥ·ʔ-ports")
|
||||
)
|
||||
|
||||
(lib_symbols
|
||||
)
|
||||
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue